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18-bit, 1 msps pulsar 7.0 mw adc in msop/qfn ad7982 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features 18-bit resolution with no missing codes throughput: 1 msps low power dissipation 7.0 mw at 1 msps 70 w at 10 ksps inl: 1 lsb typical, 2 lsb maximum dynamic range: 99 db true differential analog input range: v ref 0 v to v ref with v ref between 2.5 v to 5.0 v allows use of any input range easy to drive with the ada4941 no pipeline delay single-supply 2.5 v operation wi th 1.8 v/2.5 v/3 v/5 v logic interface serial interface spi?-/qspi?-/microwire?-/dsp-compatible ability to daisy-chain multiple adcs and busy indicator 10-lead package: msop (msop-8 size) and 3 mm 3 mm qfn (lfcsp), sot-23 size applications battery-powered equipment data acquisition systems medical instruments seismic data acquisition systems application diagram example ad7982 ref gnd vdd in+ in? vio sdi sck sdo cnv 1.8v to 5v ada4941 3- or 4-wire interface (spi, cs daisy chain) 2.5v to 5 v 2.5 v 06513-001 10v, 5v, .. figure 1. general description the ad7982 is an 18-bit, successive approximation, analog-to- digital converter (adc) that operates from a single power supply, vdd. it contains a low power, high speed, 18-bit sampling adc and a versatile serial interface port. on the cnv rising edge, the ad7982 samples the voltage difference between the in+ and in? pins. the voltages on these pins usually swing in opposite phases between 0 v and v ref . the reference voltage, ref, is applied externally and can be set independent of the supply voltage, vdd. its power scales linearly with throughput. the spi-compatible serial interface also features the ability, using the sdi input, to daisy-chain several adcs on a single 3-wire bus and provides an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, and 5 v logic, using the separate vio supply. the ad7982 is available in a 10-lead msop or a 10-lead qfn (lfcsp) with operation specified from ?40c to +85c. table 1. msop, qfn (lfcsp) 14-/16-/18-bit pulsar? adcs type 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 18-bit true differential ad7691 ad7690 ad7982 ada4941 ad7984 ada4841 16-bit true differential ad7684 ad7687 ad7688 ada4941 ad7693 ada4841 16-bit pseudo differential ad7680 ad7685 ad7686 ad7980 ada4841 ad7683 ad7694 14-bit pseudo differential ad7940 ad7942 ad7946 ada4841
ad7982 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 application diagram example ........................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 ter mi nolo g y ...................................................................................... 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 12 circuit information .................................................................... 12 converter operation .................................................................. 12 typical connection diagram ................................................... 13 analog inputs .............................................................................. 14 driver amplifier choice ........................................................... 14 single-to-differential driver .................................................... 15 voltage reference input ............................................................ 15 power supply ............................................................................... 15 digital interface .......................................................................... 16 cs mode, 3-wire without busy indicator ............................. 17 cs mode, 3-wire with busy indicator .................................... 18 cs mode, 4-wire without busy indicator ............................. 19 cs mode, 4-wire with busy indicator .................................... 20 chain mode without busy indicator ...................................... 21 chain mode with busy indicator ............................................. 22 application hints ........................................................................... 23 layout .......................................................................................... 23 evaluating ad7982 performance ............................................. 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 10/07rev. 0 to rev. a changes to table 1 and layout ....................................................... 1 changes to table 2............................................................................ 3 changes to layout ............................................................................ 5 changes to layout ............................................................................ 6 changes to figure 5.......................................................................... 7 changes to figure 18 and figure 20............................................. 11 changes to figure 23...................................................................... 13 changers to figure 26 .................................................................... 15 changes to digital interface section............................................ 16 changes to figure 38...................................................................... 21 changes to figure 40...................................................................... 22 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 3/07revision 0: initial version
ad7982 rev. a | page 3 of 24 specifications vdd = 2.5 v, vio = 2.3 v to 5.5 v, ref = 5 v, t a = ?40c to +85c, unless otherwise noted. table 2. parameter conditions min typ max unit resolution 18 bits analog input voltage range in+ ? in? ?v ref +v ref v absolute input voltage in+, in? ?0.1 v ref + 0.1 v common-mode input range in+, in? v ref 0.475 v ref 0.5 v ref 0.525 v analog input cmrr f in = 450 khz 67 db leakage current at 25c acquisition phase 200 na input impedance see the analog input s section accuracy no missing codes 18 bits differential linearity error ?0.85 0.5 +1.5 lsb 1 integral linearity error ?2 1 +2 lsb 1 transition noise ref = 5 v 1.05 lsb 1 gain error, t min to t max 2 ?0.023 +0.004 +0.023 % of fs gain error temperature drift 1 ppm/c zero error, t min to t max 2 100 +700 v zero temperature drift 0.5 ppm/c power supply rejection ratio vdd = 2.5 v 5% 90 db throughput conversion rate 0 1 msps transient response full-scale step 290 ns ac accuracy dynamic range v ref = 5 v 97 99 db 3 v ref = 2.5 v 93 db 3 oversampled dynamic range 4 f o = 1 ksps 129 db 3 signal-to-noise f in = 1 khz, v ref = 5 v, t a = 25c 95.5 98 db 3 f in = 1 khz, v ref = 2.5 v, t a = 25c 92.5 db 3 spurious-free dynamic range f in = 10 khz ?115 db 3 total harmonic distortion 5 f in = 10 khz ?120 db 3 signal-to-(noise + distortion) f in = 1 khz, v ref = 5 v, t a = 25c 97 db 3 1 lsb means least significant bit. with the 5 v input range, 1 lsb is 38.15 v. 2 see terminology section. these specifications include full te mperature range variation but not the error contribution from the external reference. 3 all specifications expressed in decibels are referred to a full-scale input fsr and tested with an input signal at 0.5 db belo w full scale, unless otherwise specified. 4 dynamic range is obtained by oversamp ling the adc running at a throughput f s of 1 msps followed by postdigital filtering with an output word rate of f o . 5 tested fully in production at f in = 1 khz.
ad7982 rev. a | page 4 of 24 vdd = 2.5 v, vio = 2.3 v to 5.5 v, ref = 5 v, t a = ?40c to +85c, unless otherwise noted. table 3. parameter conditions min typ max unit reference voltage range 2.4 5.1 v load current 1 msps, ref = 5 v 350 a sampling dynamics ?3 db input bandwidth 10 mhz aperture delay vdd = 2.5 v 2 ns digital inputs logic levels v il vio > 3 v C0.3 +0.3 vio v v ih vio > 3 v 0.7 vio vio + 0.3 v v il vio 3 v C0.3 +0.1 vio v v ih vio 3 v 0.9 vio vio + 0.3 v i il ?1 +1 a i ih ?1 +1 a digital outputs data format serial 18 bits, twos complement pipeline delay conversion results available immediately after completed conversion v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies vdd 2.375 2.5 2.625 v vio specified performance 2.3 5.5 v vio range 1.8 5.5 v standby current 1 , 2 vdd and vio = 2.5 v, 25c 0.35 a power dissipation 10 ksps throughput 70 86 w 1 msps throughput 7.0 8.6 mw energy per conversion 7.0 nj/sample temperature range 3 specified performance t min to t max ?40 +85 c 1 with all digital inputs forced to vio or gnd as required. 2 during acquisition phase. 3 contact an analog devices, inc. sales representative for the extended temperature range.
ad7982 rev. a | page 5 of 24 timing specifications t a = ?40c to +85c, vdd = 2.37 v to 2.63 v, vio = 2.3 v to 5.5 v, unless otherwise noted. 1 table 4. parameter symbol min typ max unit conversion time: cnv rising edge to data available t conv 500 710 ns acquisition time t acq 290 ns time between conversions t cyc 1000 ns cnv pulse width ( cs mode) t cnvh 10 ns sck period ( cs mode) t sck vio above 4.5 v 10.5 ns vio above 3 v 12 ns vio above 2.7 v 13 ns vio above 2.3 v 15 ns sck period (chain mode) t sck vio above 4.5 v 11.5 ns vio above 3 v 13 ns vio above 2.7 v 14 ns vio above 2.3 v 16 ns sck low time t sckl 4.5 ns sck high time t sckh 4.5 ns sck falling edge to data remains valid t hsdo 3 ns sck falling edge to data valid delay t dsdo vio above 4.5 v 9.5 ns vio above 3 v 11 ns vio above 2.7 v 12 ns vio above 2.3 v 14 ns cnv or sdi low to sdo d15 msb valid ( cs mode) t en vio above 3 v 10 ns vio above 2.3 v 15 ns cnv or sdi high or last sck falling edge to sdo high impedance ( cs mode) t dis 20 ns sdi valid setup time from cnv rising edge t ssdicnv 5 ns sdi valid hold time from cnv rising edge ( cs mode) t hsdicnv 2 ns sdi valid hold time from cnv rising edge (chain mode) t hsdicnv 0 ns sck valid setup time from cnv rising edge (chain mode) t ssckcnv 5 ns sck valid hold time from cnv rising edge (chain mode) t hsckcnv 5 ns sdi valid setup time from sck falling edge (chain mode) t ssdisck 2 ns sdi valid hold time from sck falling edge (chain mode) t hsdisck 3 ns sdi high to sdo high (chain mode with busy indicator) t dsdosdi 15 ns 1 see figure 2 and figure 3 for load conditions. 500a i ol 500a i oh 1.4v to sdo c l 20pf 06513-002 figure 2. load circuit fo r digital interface timing x% vio 1 y% vio 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for vio 3.0v, x = 90, and y = 10; for vio > 3.0v, x = 70, and y = 30. 2 minimum v ih and maximum v il used. see digital inputs specifications in table 3. 06513-003 figure 3. voltage levels for timing
ad7982 rev. a | page 6 of 24 absolute maximum ratings table 5. parameter rating analog inputs in+, in? to gnd 1 ?0.3 v to v ref + 0.3 v or 130 ma supply voltage ref, vio to gnd ?0.3 v to +6.0 v vdd to gnd ?0.3 v to +3.0 v vdd to vio +3 v to ?6 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 10-lead msop 200c/w 10-lead qfn (lfcsp_wd) 48.7c/w jc thermal impedance 10-lead msop 44c/w 10-lead qfn (lfcsp_wd) 2.96c/w lead temperatures vapor phase (60 sec) 215c infrared (15 sec) 220c 1 see the analog input s section for an explanation of in+ and in?. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7982 rev. a | page 7 of 24 pin configurations and function descriptions ref 1 vdd 2 in+ 3 in? 4 gnd 5 vio 10 sdi 9 sck 8 sdo 7 cnv 6 ad7982 top view (not to scale) 06513-004 figure 4. 10-lead msop pin configuration 06513-005 1 ref 2 vdd 3 in+ 4 in? 5 gnd 10 vio 9sdi 8sck 7sdo 6 cnv ad7982 top view figure 5. 10-lead qfn (lfcsp) pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 1 ref ai reference input voltage. the ref range is 2.4 v to 5.1 v. this pin is referred to the gnd pin and should be decoupled closely to the gnd pin with a 10 f capacitor. 2 vdd p power supply. 3 in+ ai differential positive analog input. 4 in? ai differential negative analog input. 5 gnd p power supply ground. 6 cnv di convert input. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the part: chain mode or cs mode. in cs mode, the sdo pin is enabled when cnv is low. in chain mode, the data should be read when cnv is high. 7 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 8 sck di serial data clock input. when the part is selected, the conversion result is shifted out by this clock. 9 sdi di serial data input. this input provides multiple fe atures. it selects the interface mode of the adc as follows: chain mode is selected if sdi is low during the cnv risi ng edge. in this mode, sdi is used as a data input to daisy-chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 18 sck cycles. cs mode is selected if sdi is high during the cnv risi ng edge. in this mode, either sdi or cnv can enable the serial output signals when low. if sdi or cnv is lo w when the conversion is complete, the busy indicator feature is enabled. 10 vio p input/output interface digital power. nominally at the same supply as the host interface (1.8 v, 2.5 v, 3 v, or 5 v). 1 ai = analog input, di = digital input, do = digital output, and p = power.
ad7982 rev. a | page 8 of 24 terminology integral nonlinearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 22 ). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, from the actual voltage producing the midscale output code, that is, 0 lsb. gain error the first transition (from 100 ... 00 to 100 ... 01) should occur at a level ? lsb above nominal negative full scale (?4.999981 v for the 5 v range). the last transition (from 011 10 to 011 11) should occur for an analog voltage 1? lsb below the nominal full scale (+4.999943 v for the 5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad as follows enob = ( sinad db ? 1.76)/6.02 and is expressed in bits. noise-free code resolution noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as noise-free code resolution = log 2 (2 n / peak-to-peak noise ) and is expressed in bits. effective resolution effective resolution is calculated as effective resolution = log 2 (2 n / rms input noise ) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. it is measured with a signal at ?60 dbf so that it includes all noise sources and dnl artifacts. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the nyquist frequency, including harmonics but excluding dc. the value of sinad is expressed in decibels. aperture delay aperture delay is the measure of the acquisition performance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. transient resp onse transient response is the time required for the adc to accurately acquire its input after a full-scale step function is applied.
ad7982 rev. a | page 9 of 24 typical performance characteristics vdd = 2.5 v, ref = 5.0 v, vio = 3.3 v. 06513-006 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 inl (lsb) 0 65536 131072 196608 262144 code positive inl: +0.79 lsb negative inl: ?0.68 lsb figure 6. integral nonlinearity vs. code 60000 50000 40000 30000 20000 10000 0 counts 3fff0 3fff2 3fff4 3fff6 3fff8 3fffa 3fffc code in hex 00 29 745 881 43 0 06513-007 0 7795 29064 50975 32476 9064 figure 7. histogram of a dc input at the code center 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 0 100 200 300 400 500 frequency (khz) amplitude (db of full scale) 06513-008 f s = 1msps f in = 2khz snr = 97.3db thd = ?121.8db sfdr = 120.2db sinad = 97.3db figure 8. fft plot 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 0 65536 131072 196608 262144 code dnl (lsb) 06513-009 positive inl: +0.46 lsb negative inl: ?0.49 lsb figure 9. differential nonlinearity vs. code 50000 45000 40000 35000 30000 25000 0 counts 012 34 56789a d code in hex 007 145 70 0 06513-010 20000 15000 10000 5000 222 cb 16682 44806 43239 20013 3158 2793 figure 10. histogram of a dc input at the code transition 100 99 98 97 96 95 94 93 92 91 90 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 input level (db) snr (db referred to full scale) 06513-032 figure 11. snr vs. input level
ad7982 rev. a | page 10 of 24 100 95 90 85 80 snr, sinad (db) 06513-034 2.25 2.75 3.25 3.75 4.25 4.75 5.25 reference voltage (v) 18 17 16 15 14 enob (bits) enob snr, sinad figure 12. snr, sinad, and enob vs. reference voltage 100 98 96 94 92 90 snr (db) ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) 06513-042 figure 13. snr vs. temperature 100 95 90 85 80 0.1 1 10 100 1000 frequency (khz) sinad (db) 06513-031 figure 14. sinad vs. frequency 06513-033 ? 100 ?105 ?110 ?115 ?120 ?125 ?130 thd (db) 2.25 2.75 3.25 3.75 4.25 4.75 5.25 reference voltage (v) 130 125 120 115 110 105 100 sfdr (db) thd sfdr figure 15. thd, sfdr vs. reference voltage ? 115 ?117 ?119 ?121 ?123 ?125 thd (db) ?55 ?35 ?15 5 25 45 65 85 105 125 temperature (c) 06513-041 figure 16. thd vs. temperature ? 80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 ?120 ?125 0.1 1 10 100 1000 frequency (khz) thd (db) 06513-030 figure 17. thd vs. frequency
ad7982 rev. a | page 11 of 24 06513-036 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 operating currents (ma) 2.425 2.475 supply voltage (v) 2.375 2.525 2.575 2.625 i vdd i ref i vio figure 18. operating currents vs. supply voltage 06513-038 8 7 6 5 4 3 2 1 0 power-down currents (a) ?55 ?35 ?15 5 25 temperature (c) 45 65 85 105 125 i vdd + i vio figure 19. power-down currents vs. temperature 06513-035 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 operating currents (ma) ?55 ?35 ?15 5 25 temperature (c) 45 65 85 105 125 i vdd i ref i vio figure 20. operating currents vs. temperature
ad7982 rev. a | page 12 of 24 theory of operation comp control logic switches control busy output code cnv c c 2c 65,536c 4c 131,072c lsb sw+ msb lsb sw? msb c c 2c 65,536c 4c 131,072c in+ ref g nd in? 06513-011 figure 21. adc simplified schematic circuit information the ad7982 is a fast, low power, single-supply, precise, 18-bit adc using a successive approximation architecture. the ad7982 is capable of converting 1,000,000 samples per second (1 msps) and powers down between conversions. when operating at 10 ksps, for example, it typically consumes 70 w, making it ideal for battery-powered applications. the ad7982 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7982 can be interfaced to any 1.8 v to 5 v digital logic family. it is available in a 10-lead msop or a tiny 10-lead qfn (lfcsp) that allows space savings and flexible configurations. it is pin-for-pin-compatible with the 16-bit ad7980 . converter operation the ad7982 is a successive approximation adc based on a charge redistribution dac. figure 21 shows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 18 binary-weighted capacitors, which are connected to the two comparator inputs. during the acquisition phase, terminals of the array tied to the input of the comparator are connected to gnd via sw+ and sw?. all independent switches are connected to the analog inputs. therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in? inputs. when the acquisition phase is complete and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the inputs in+ and in? captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become un balanced. by switching each element of the capacitor array between gnd and ref, the comparator input varies by binary-weighted voltage steps (v ref /2, v ref /4 ... v ref /262,144). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase, and the control logic generates the adc output code and a busy signal indicator. because the ad7982 has an on-board conversion clock, the serial clock, sck, is not required for the conversion process.
ad7982 rev. a | page 13 of 24 transfer functions the ideal transfer characteristic for the ad7982 is shown in figure 22 and table 7 . 100...000 100...001 100...010 011...101 011...110 011...111 adc code (twos complement) analog input +fsr ? 1.5 lsb +fsr ? 1 lsb ?fsr + 1 lsb ?fsr ?fsr + 0.5 lsb 06513-012 figure 22. adc ideal transfer function table 7. output codes and ideal input voltages description analog input v ref 5 v digital output code (he) fsr C 1 lsb +4.999962 v 0x1ffff 1 midscale + 1 lsb +38.15 v 0x00001 midscale 0 v 0x00000 midscale C 1 lsb ?38.15 v 0x3ffff Cfsr + 1 lsb ?4.999962 v 0x20001 Cfsr ?5 v 0x20000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). typical connection diagram figure 23 shows an example of the recommended connection diagram for the ad7982 when multiple supplies are available. 2.7nf 20 ? v? 0 to vref v+ 4 2.7nf 20 ? v? v ref to 0 v+ 4 10f 2 ref 1 ref vdd vio gnd in+ in? sdi sck sdo cnv ad7982 100nf 100nf 3-wire interface 2.5v 1.8v to 5v v+ ada4841 2, 3 notes 1 see voltage reference input section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). see recommended layout figure 41 and figure 42. 3 see driver amplifier choice section. 4 optional filter. see analog input section. 06513-013 figure 23. typical application diagram with multiple supplies
ad7982 rev. a | page 14 of 24 analog inputs figure 24 shows an equivalent circuit of the input structure of the ad7982. the two diodes, d1 and d2, provide esd protection for the analog inputs, in+ and in?. care must be taken to ensure that the analog input signal does not exceed the reference input voltage (ref) by more than 0.3 v. if the analog input signal exceeds this level, the diodes become forward biased and start conducting current. these diodes can handle a forward-biased current of 130 ma maximum. however, if the supplies of the input buffer (for example, the supplies of the ada4841 in figure 23 ) are different from those of the ref, the analog input signal may eventually exceed the supply rails by more than 0.3 v. in such a case (for example, an input buffer with a short- circuit), the current limitation can be used to protect the part. c pin ref r in c in d1 d2 in+ or in? gnd 06513-014 figure 24. equivalent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in?. by using these differential inputs, signals common to both inputs are rejected. 90 85 80 75 70 65 60 1 10 100 1000 10000 frequency (khz) cmrr (db) 06513-040 figure 25. analog input cmrr vs. frequency during the acquisition phase, the impedance of the analog inputs (in+ or in?) can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 and is a lumped component composed of serial resistors and the on resistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the sampling phase, where the switches are closed, the input impedance is limited to c pin . r in and c in make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits noise. when the source impedance of the driving circuit is low, the ad7982 can be driven directly. large source impedances significantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier choice although the ad7982 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noise performance of the ad7982. the noise from the driver is filtered by the ad7982 analog input circuits 1-pole, low- pass filter made by r in and c in or by the external filter, if one is used. because the typical noise of the ad7982 is 40 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 )( 2 40 40 log20 n 3db loss nef snr where: f C3db is the input bandwidth, in megahertz, of the ad7982 (10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, 1 in buffer configuration). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver should have a thd perfor- mance commensurate with the ad7982. ? for multichannel multiplexed applications, the driver amplifier and the ad7982 analog input circuit must settle for a full-scale step onto the capacitor array at an 18-bit level (0.0004%, 4 ppm). in the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. this may differ significantly from the settling time at an 18-bit level and should be verified prior to driver selection. table 8. recommended driver amplifiers amplifier typical application ada4941 very low noise, low power, single to differential ada4841 very low noise, small, and low power ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8655 5 v single supply, low noise ad8605 , ad8615 5 v single supply, low power
ad7982 rev. a | page 15 of 24 single-to-differ ential driver for applications using a single-ended analog signal, either bipolar or unipolar, the ada4941 single-ended-to-differential driver allows for a differential input to the part. the schematic is shown in figure 26 . r1 and r2 set the attenuation ratio between the input range and the adc range (v ref ). r1, r2, and c f are chosen depending on the desired input resistance, signal bandwidth, antialiasing, and noise contribution. for example, for the 10 v range with a 4 k impedance, r2 = 1 k and r1 = 4 k. r3 and r4 set the common mode on the in? input, and r5 and r6 set the common mode on the in+ input of the adc. the common mode should be close to v ref /2. for example, for the 10 v range with a single supply, r3 = 8.45 k, r4 = 11.8 k, r5 = 10.5 k, and r6 = 9.76 k. 06513-015 20? 20? 10f r1 100nf +2.5v +5v ref +5.2v ?0.2v c f r2 r4 r6 10v, 5v, .. r3 r5 ref vdd gnd in+ in? ad7982 2.7nf 2.7nf ada4941 in fb outp outn ref 100nf figure 26. single-ended-to- differential driver circuit voltage reference input the ad7982 voltage reference input, ref, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the ref and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source (for example, a reference buffer using the ad8031 or the ad8605 ), a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr43x reference. if desired, a reference decoupling capacitor with values as small as 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and gnd pins. power supply the ad7982 uses two power supply pins: a core supply (vdd) and a digital input/output interface supply (vio). vio allows direct interface with any logic between 1.8 v and 5.5 v. to reduce the number of supplies needed, vio and vdd can be tied together. the ad7982 is independent of power supply sequencing between vio and vdd. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 27 . 95 90 85 80 75 70 65 60 psrr (db) 1 10 100 1000 frequency (khz) 06513-039 figure 27. psrr vs. frequency to ensure optimum performance, vdd should be roughly half of ref, the voltage reference input. for example, if ref is 5.0 v, vdd should be set to 2.5 v (5%). the ad7982 powers down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. this makes the part ideal for low sampling rates (even of a few hertz) and low battery-powered applications. 06513-037 10.000 1.000 0.100 0.010 0.001 oper a ting currents (ma) 100000 sampling rate (sps) 10000 1000000 i vdd i vio i ref figure 28. operating currents vs. sampling rate
ad7982 rev. a | page 16 of 24 digital interface although the ad7982 has a reduced number of pins, it offers flexibility in its serial interface modes. when in cs mode, the ad7982 is compatible with spi, qspi, digital hosts, and dsps. in this mode, the ad7982 can use either a 3-wire or 4-wire interface. a 3-wire interface using the cnv, sck, and sdo signals minimizes wiring connections useful, for instance, in isolated applications. a 4-wire interface using the sdi, cnv, sck, and sdo signals allows cnv, which initiates the conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. when in chain mode, the ad7982 provides a daisy-chain feature using the sdi input for cascading multiple adcs on a single data line similar to a shift register. the mode in which the part operates depends on the sdi level when the cnv rising edge occurs. the cs mode is selected if sdi is high, and the chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, the chain mode is always selected. in either mode, the ad7982 offers the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must timeout the maximum conversion time prior to readback. the busy indicator feature is enabled ? in the cs mode if cnv or sdi is low when the adc conversion ends (see figure 32 and figure 36 ). ? in the chain mode if sck is high during the cnv rising edge (see figure 40 ).
ad7982 rev. a | page 17 of 24 cs mode, 3-wire without busy indicator this mode is usually used when a single ad7982 is connected to an spi-compatible digital host. the connection diagram is shown in figure 29 , and the corresponding timing is given in figure 30 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. once a conversion is initiated, it continues until completion irrespective of the state of cnv. this can be useful, for instance, to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7982 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 18 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. ad7982 sdi sdo cnv sck convert data in clk digital host vio 06513-016 figure 29. cs mode, 3-wire without busy indicator connection diagram (sdi high) sdo d17 d16 d15 d1 d0 t dis sck 123 161718 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq t en 06513-017 figure 30. cs mode, 3-wire without busy indicator serial interface timing (sdi high)
ad7982 rev. a | page 18 of 24 cs mode, 3-wire with busy indicator this mode is usually used when a single ad7982 is connected to an spi-compatible digital host having an interrupt input. the connection diagram is shown in figure 31 , and the corresponding timing is given in figure 32 . with sdi tied to vio, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data reading controlled by th e digital host. the ad7982 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 19 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. if multiple ad7982s are selected at the same time, the sdo output pin handles this contention without damage or induced latch-up. meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. ad7982 sdi sdo cnv sck convert data in clk digital host vio 06513-018 irq vio 47k ? figure 31. cs mode, 3-wire with busy indicator connection diagram (sdi high) sdo d17 d16 d1 d0 t dis sck 1 2 3 17 18 19 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition sdi = 1 t cnvh t acq 06513-019 figure 32. cs mode, 3-wire with busy indicator serial interface timing (sdi high)
ad7982 rev. a | page 19 of 24 cs mode, 4-wire without busy indicator this mode is usually used when multiple ad7982s are connected to an spi-compatible digital host. a connection diagram example using two ad7982s is shown in figure 33 , and the corresponding timing is given in figure 34 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7982 enters the acquisition phase and powers down. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 18 th sck falling edge or when sdi goes high (whichever occurs first), sdo returns to high impedance and another ad7982 can be read. ad7982 sdi sdo cnv sck convert data in clk digital host 06513-020 cs1 cs2 ad7982 sdi sdo cnv sck figure 33. cs mode, 4-wire without busy indicator connection diagram sdo d17 d16 d15 d1 d0 t dis sck 123 343536 t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi(cs1) cnv t ssdicnv t hsdicnv d1 16 17 t sck t sckl t sckh d0 d17 d16 19 20 18 sdi(cs2) 06513-021 figure 34. cs mode, 4-wire without busy indicator serial interface timing
ad7982 rev. a | page 20 of 24 cs mode, 4-wire with busy indicator this mode is usually used when a single ad7982 is connected to an spi-compatible digital host with an interrupt input and when it is desired to keep cnv, which is used to sample the analog input, independent of the signal used to select the data reading. this independence is particularly important in applications where low jitter on cnv is desired. the connection diagram is shown in figure 35 , and the corresponding timing is given in figure 36 . with sdi high, a rising edge on cnv initiates a conversion, selects the cs mode, and forces sdo to high impedance. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexers, but sdi must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high impedance to low impedance. with a pull-up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7982 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided it has an acceptable hold time. after the optional 19 th sck falling edge or sdi going high (whichever occurs first), sdo returns to high impedance. ad7982 sdi sdo cnv sck convert data in clk digital host 06513-022 irq vio 47k ? cs1 figure 35. cs mode, 4-wire with busy indicator connection diagram sdo d17 d16 d1 d0 t dis sck 1 2 3 171819 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv 06513-023 figure 36. cs mode, 4-wire with busy indicator serial interface timing
ad7982 rev. a | page 21 of 24 chain mode without busy indicator this mode can be used to daisy-chain multiple ad7982s on a 3-wire serial interface. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7982s is shown in figure 37 , and the corresponding timing is given in figure 38 . when sdi and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects the chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo and the ad7982 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 18 n clocks are required to read back the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7982s in the chain, provided the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. convert data in clk digital host 0 6513-024 ad7982 sdi sdo cnv b sck ad7982 sdi sdo cnv a sck figure 37. chain mode without busy indicator connection diagram sdo a = sdi b d a 17 d a 16 d a 15 sck 1 2 3 343536 t ssdisck t hsdisck t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 16 17 t sck t sckl t sckh d a 0 19 20 18 sdi a = 0 sdo b d b 17 d b 16 d b 15 d a 1 d b 1d b 0d a 17 d a 16 t hsdo t dsdo t ssckcnv t hsckcnv d a 0 06513-025 figure 38. chain mode without busy indicator serial interface timing
ad7982 rev. a | page 22 of 24 chain mode with busy indicator this mode can also be used to daisy-chain multiple ad7982s on a 3-wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three ad7982s is shown in figure 39 , and the corresponding timing is given in figure 40 . when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects the chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo pin of the adc closest to the digital host (see the ad7982 adc labeled c in figure 39 ) is driven high. this transition on sdo can be used as a busy indicator to trigger the data readback controlled by the digital host. the ad7982 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 18 n + 1 clocks are required to read back the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7982s in the chain, provided the digital host has an acceptable hold time. convert data in clk digital host 06513-026 ad7982 sdi sdo cnv c sck ad7982 sdi sdo cnv a sck irq ad7982 sdi sdo cnv b sck figure 39. chain mode with bu sy indicator connection diagram sdo a = sdi b d a 17 d a 16 d a 15 sck 123 39 53 54 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 417 t sck t sckh t sckl d a 0 19 38 18 sdo b = sdi c d b 17 d b 16 d b 15 d a 1 d b 1d b 0d a 17 d a 16 55 t ssdisck t hsdisck t hsdo t dsdo sdo c d c 17 d c 16 d c 15 d a 1d a 0 d c 1d c 0d a 16 21 35 36 20 37 d b 1d b 0d a 17 d b 17 d b 16 t dsdosdi t ssckcnv t hsckcnv d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi 06513-027 figure 40. chain mode with busy indicator serial interface timing
ad7982 rev. a | page 23 of 24 application hints layout the printed circuit board that houses the ad7982 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7982, with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the ad7982 is used as a shield. fast switching signals, such as cnv or clocks, should not run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground plane should be used. it can be common or split between the digital and analog sections. in the latter case, the planes should be joined underneath the ad7982s. the ad7982 voltage reference input ref has a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the ref and gnd pins and connecting them with wide, low impedance traces. finally, the power supplies vdd and vio of the ad7982 should be decoupled with ceramic capacitors, typically 100 nf, placed close to the ad7982 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. an example of layout following these rules is shown in figure 41 and figure 42 . evaluating ad7982 performance other recommended layouts for the ad7982 are outlined in the documentation of the evaluation board for the ad7982 ( eval-ad7982cbz ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd3 . 06513-028 ad7982 figure 41. example layout of the ad7982 (top layer) 06513-029 figure 42. example layout of the ad7982 (bottom layer)
ad7982 rev. a | page 24 of 24 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 43. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 062507-b top view 8 1 5 4 0.30 0.23 0.18 exposed pad (bottom view) pin 1 index area 3.00 bsc sq seating plane 0.80 0.75 0.70 0.20 ref 0.05 max 0.02 nom 0.80 max 0.55 nom 1.74 1.64 1.49 2.48 2.38 2.23 0.50 0.40 0.30 0.50 bsc p i n 1 i n d i c a t o r ( r 0 . 1 9 ) figure 44. 10-lead lead frame chip scale package [qfn (lfcsp_wd)] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters ordering guide model temperature range package description pa ckage option ordering quantity branding ad7982brmz 1 ?40c to +85c 10-lead msop rm-10 tube, 50 c5f AD7982BRMZRL7 1 ?40c to +85c 10-lead msop rm-10 reel, 1000 c5f ad7982bcpz 1 ?40c to +85c 10-lead qfn (lfcsp_wd) cp-10-9 tube, 75 c5f ad7982bcpz-rl7 1 ?40c to +85c 10-lead qfn (lfcsp_wd) cp-10-9 reel, 1000 c5f ad7982bcpz-rl 1 ?40c to +85c 10-lead qfn (lfcsp_wd) cp-10-9 reel, 5000 c5f eval-ad7982cbz 1 , 2 evaluation board eval-control brd3z 3 controller board 1 z = rohs compliant part. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd3 for evaluation/demonstrat ion purposes. 3 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designator. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06513C0C10/07(a)

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